Apparatus for the digital control of analog signal

ABSTRACT

A digital-analog converter electrically effecting sequential switching between a reference voltage point and each of the connection points formed in a circuit network composed of serially connected impedance elements for taking out desired analog quantity such as signal voltage level, impedance value or the like in response to the application of control pulses, which comprises in combination memory circuits such as R-S flip-flops, gate circuits such as NAND gates and delay circuit such as integration circuits, capacitors and the likes. The provision of the delay circuits, in particular, advantageously facilitates the setting for the initial operation state and the preparation for the sequential switching.

BACKGROUND OF THE INVENTION

This invention relates to an apparatus for the digital control of an analog signal and, in particular, to a circuit arrangement for varying an analog quantity such as voltage, an impedance or the like.

Adjustments of the audio volume, color saturation, contrast, brightness and the like in various receivers such as a television receiver are sometimes performed by the use of a remote control apparatus instead of manually operating each of the adjustment knobs provided as part of a receiver. In such a remote control adjustment, a transmitter and a receiver are usually employed for the remote control. The transmitter may be operated by a viewer and the receiver is incorporated in the cabinet of a television receiver proper. The transmitter of the remote control apparatus is manipulated by the television viewer to send instruction signals, which are aerially transmitted as ultrasonic waves or as electric waves or the transmission directly may be through wire means to the television receiver. Corresponding to the types of the instruction signals, the receiver of the remote control apparatus generates pulse-shaped control signals and applies these control signals to the circuits to be controlled such as a volume control circuit, a color saturation control circuit and the like. Since the above described circuits to be controlled are adapted to operate in such a manner that they vary their analog output such as a voltage, an impedance or the like in accordance with the number of pulses in the control signals, a digital control is conventionally used for controlling such circuits. The digital control devices of this type employed so far, are adapted to count and store the a number of pulses by means of an up-down counter, and to effect a switching among the electronic switches provided in a resistor circuit network in response to the counted output to thereby provide voltages from said resistor circuit network corresponding to said counted pulses. The digital control devices of the type described are, however, expensive and hence not suited for use in apparatus used in the home such as television receivers.

SUMMARY OF THE INVENTION

An object of this invention is to provide a simplified circuit for varying an analog quantity such as the voltage level of an AC current signal, a DC voltage level, an impedance value or the like.

Another object of this invention is to provide a circuit arrangement which is economical and suited for the mass production by the use of IC components.

A further object of this invention is to provide a circuit arrangement which is suitable for the remote control of the adjustment for the audio volume, the color saturation, the brightness or the like of a television receiver.

In this invention, for attaining the foregoing objects, a circuit network having a plurality of impedance elements, for instance, serially connected resistor elements, is connected to a further plurality of memory circuits, for example, composed of R-S flip-flops which correspond to each of the connection points between said impedance elements so as to apply a reference voltage or a ground potential to any one of said connection points. The memory circuits are adapted so that a "set" input signal is always applied to a set input terminal of the first memory circuit when a first control signal arrives and a reset input signal is always applied to the reset input terminal of the final memory circuit when a second control signal arrives. The set input terminals and the reset input terminals of other memory circuits are controlled by gate circuits. A voltage generated at one output terminal of a pair of output terminals of a memory circuit, is applied through a delay circuit to a gate circuit at the reset input of the succeeding memory circuit. A voltage generated at the other output terminal of said pair of output terminals is applied through a similar delay circuit to a gate circuit at the reset input of the preceeding memory circuit thereby providing input signals for each of the gates. The memory circuits of a plurality of stages are divided into two group. Each group is provided with optional stages including delay circuits for delaying the "set" input signals to the memory circuits of the group including the memory circuit of the first stage. Each group is further provided with delay circuits for delaying the "reset" inputs to the memory circuit of the group including the memory circuit of the final stage. These features establish the initial operation condition of the digital control circuit.

DESCRIPTION OF THE ACCOMPANYING DRAWINGS

FIG. 1 is a circuit diagram of a preferred embodiment of this invention;

FIG. 2 and FIG. 3 are truth tables for showing the operation conditions of the circuit in each of their stabilized stages;

FIG. 4 is a circuit diagram of another preferred embodiment of this invention; and

FIG. 5 and FIG. 6 are examples for the circuit connections of the impedance circuit network for use in the circuit shown in FIG. 1 or in FIG. 2.

DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to the circuit shown in FIG. 1, a terminal A₁ is an input terminal to which an audio signal voltage is applied for example. Resistors R₁ through R₅ are connected in series between the input terminal A₁ and ground. To each of the connection points J₁ to J₄ formed between adjacent resistors connected in series, is connected the respective terminal of the output terminals Q₁₁, Q₂₁, Q₃₁ and Q₄₁ of the circuits enclosed by dashed lines denoted as F₁ to F₄. Each of the circuits F₁ to F₄ has a similar construction and includes a well known R-S flip-flop. Referring to the construction of the flip-flops taking F₁ as a representative, the circuit comprises NAND gates N₁₁ and N₁₂. The output terminal Q₁₁ of the NAND gate N₁₁ is connected to one of the input terminals of the NAND gate N₁₂ and the output terminal Q₁₂ of said NAND gate N₁₂ is connected to one of the input terminals of the NAND gate N₁₁. The input terminal S₁ of the NAND gate N₁₁ forms a set terminal of the flip-flop F₁. The input terminal r₁ of the NAND gate N₁₂ forms a reset terminal. When the set input terminal S₁ has a low voltage level, a stabilized state, that is, a set state is established wherein the output terminal Q₁₁ provides a high voltage level and the output terminal Q₁₂ provides a low voltage level. When the reset terminal r₁ is set at a low voltage level, a reset state is attained wherein the output terminals Q₁₁ and Q₁₂ respectively provide a voltage opposite to the foregoing state.

The set terminal S₁ of the flip-flop F₁ is connected with an output terminal of a gate circuit G₁₁ and the reset terminal r₁ is connected with an output terminal of a gate circuit G₁₂. The gate circuit G₁₁ is connected of a NAND gate and has a gate input terminal g₁₁ and a set input terminal s₁₁. Each of the gate circuits G₂₁, G₂₂, G₃₁, G₃₂, G₄₁ and G₄₂ has a similar construction. A circuit T₁₁ including a resistor R₁₁ and a capacitor C₁₁ connected in series, is connected between the output terminal Q₁₁ of the flip-flop F₁ and ground. The connection point between the resistor R₁₁ and the capacitor C₁₁ is connected to the gate terminal g₂₁ of the gate circuit G₂₁. The circuit T₁₁ is an integration circuit and constitutes a delay circuit which delays the output signals of the output terminal Q₁₁ and applies the delayed output signals to the terminal g₂₁ as an input signal. The circuits having the same function as that of the delay circuit T₁₁ are shown as blocks T₂₁, T₃₁, T₂₂, T₃₂ and T₄₂. The delay circuit T₂₁ is connected between the output terminal Q₂₁ of the flip-flop F₂ and the input terminal g₃₁ of the gate circuit G₃₁. The delay circuit T₃₁ is connected between the output terminal Q₃₁ of the flip-flop F₃ and terminal g₄₁ of the gate circuit G₄₁. The delay circuit T₂₂ is connected between the output terminal Q₂₂ of the flip-flop F₂ and the terminal g₁₂ of the gate circuit G₁₂. The delay circuits T₃₂ and T₄₂ are connected respectively in a similar manner between the output terminals Q₃₂ and Q₄₂ of the flip-flops F₃ and F₄ and the terminals g₂₂ and g₃₂ of the gate circuits G₂₂ and G₃₂ respectively, as illustrated in the drawing. The input terminals g₁₁, s₁₁, s₂₁, s₃₁ and s₄₁ of the gate circuits G₁₁, G₂₁, G₃₁ and G₄₁ are connected to a common terminal U₁. The input terminals s₁₂, s₂₂, s₃₂, s₄₂ and g₄₂ of the gate circuits G₁₂, G₂₂, G₃₂ and G₄₂ are connected to the other common terminal D₁. A capacitor C₁ for delaying a high level input voltage when the same is applied, is connected between the set input terminal s₁ of the flip-flop F₁ and ground. Capacitors C₂, C₃ and C₄ which may have the same capacitance value, are respectively connected between the reset terminals r₂, r₃ and r₄ of the other flip-flop circuits and ground.

The terminal U₁ is an input terminal to which a control signal P₁ is applied and the terminal D₁ is an input terminal to which another control signal P₂ is applied. The control signals P₁ and P₂ are respectively composed of voltage pulses and are added solely or sequentially as desired. As can be seen from the description of the operation to be made later, the voltage level of the audio signal at the output terminal A₂, is increased by the application of the pulse P₁ and lowered by the application of the pulse P₂. The time constants of the capacitors C₁, C₂, C₃ and C₄ should be within such a range that the pulse voltage generated by the application of the pulse P₁ or P₂ to the output terminals of the gate circuits G₁₁, G₂₂, G₃₂ and G₄₂, can be used as set or reset input signals for flip-flop circuits with no substantial decays. Each of the time constants of the delay circuits T₁₁ · T₂₁ · T₃₁ · T₂₂ · T₃₂ and T₄₂ should be selected sufficiently greater than the pulse time width t₁ and sufficiently shorter than the pulse repeating interval t₂.

The operation of the circuit will now be described with reference to FIG. 1. The circuit operation can be understood by considering each of its typical states, that is, an initial state when a voltage from a power source is first supplied and the stabilized conditions are attained, a state after the arrival of the control signal P₁ at the terminal U₁ and the succeeding state when the control signal P₂ arrives at the terminal D₁. Since the voltages appearing at each of the terminals are either at a high level or a low level, they are referred to herein as "H" and "L" for the sake of simplicity.

(1) Initial state when only the power source voltage is applied

All of the gate inputs and the set inputs for each of the gate circuits are set at the "L" state and all of the outputs are at the "H" state. However, since a capacitor C₁ is connected between the output terminal of the gate circuit G₁₁ and ground, the voltage at the set input terminal s₁ of the flip-flop F₁ does not instantly reach the "H" state but remains at "L" until the capacitor C₁ is fully charged. On the other hand, the voltage at the reset input terminal r₁ immediately assumes the "H" state. Thus, the flip-flop F₁ establishes a set state wherein the output terminal Q₁₁ is at the "H" state.

In the flip-flop F₂, the reset terminal r₂ is also set at the "L" state by the delay function of the capacitor C₂. The output terminal Q₂₂ thus takes "H" and the other output terminal Q₂₁ takes "L" to thereby establish a reset state. In the similar manner as described above, the flip-flop circuits F₃ and F₄ also establish the reset state as the flip-flop circuit F₂. Thus, connection points J₁ becomes "H" and the other connection points J₂, J₃ and J₄ are at ground potential by way of the flip-flop circuits F₂, F₃ and F₄. Therefore, the audio signals applied through an input terminal A₁ is divided and taken off from an output terminal A₂ at a level divided by the ratio between the resistance values of the resistor R₁ and the resistor R₂. The voltage developed at the output terminal Q₁₁ is delayed in the delay circuit T.sub. 11 and then applied to the gate terminal g₂₁ of the gate circuit G₂₁ to set a "H" voltage on said terminal g₂₁. Since other flip-flop circuits assume the reset state and the output terminals Q₂₂, Q₃₂ and Q₄₂ thereof assume an "H" state. The gate terminals g₁₂, g₂₂ and g₃₂ also assume an "H" voltage or state after a delay in the delay circuits T₂₂, T₃₂ and T₄₂.

(2) A state when a first pulse P₁ is applied to the terminal U₁

In the gate G₁₁, both of the gate terminal g₁₁ and the set terminal s₁₁ are set at an "H" state to thereby develop a "L" voltage at the output thereof, which renders the voltage at the set input terminal of the flip-flop F₁ to "L". In the gate circuit G₁₂, the output terminal assumes "H" since the gate terminal g₁₂ is set to "H" as described above and the set terminal s₁₂ remains at "L". Therefore, the flip-flop F₁ establishes its set state, that is, the same state as set forth in item (1) above where the set terminal s₁ has a "L" voltage and the reset input terminal r₁ has a "H" voltage. In the gate circuit G₂₁, the gate terminal g₂₁ is kept at "H" and a pulse capable of setting the set terminal s₂₁ to "H" arrives at said terminal thereby rendering the output thereof "L". Since the reset terminal r₂ remains "H", the flip-flop F₂ establishes the set state when the set input is rendered "L" as described above, wherein the output terminal Q₂₁ takes "H" and the output terminal Q₂₂ takes "L". In the gate circuit G₃₁, since the gate terminal g₃₁ is set to "L", the output thereof remains "H" even when a pulse is applied to cause the set terminal s₃₁ to assume an "H" state. The gate circuit G₃₂ keeps its output at "H" since no pulses arrive at the set terminal s₃₂ and the gate terminal g₃₂ remains "H". As the flip-flop F₃ has been kept at its reset state since the application of the power source voltage, there is no change in the operational states. Because the output terminal Q₂₁ of the flip-flop F₂ at the preceeding stage now changes to "H", a "H" voltage is going to be applied to the gate g₃₁. However, since the delay circuit T₂₁ is interposed, the gate terminal g₃₁ is set "H" not immediately but after the pulse P₁ applied to said terminal s₃₁, has ended. As the result, the output of the gate circuit G₃₁ remains "H" to thereby keep the flip-flop F₃ from establishing the set state. Finally, in the gate circuit G₄₁, the gate terminal g₄₁ remains "L" and the set terminal s₄₁ becomes "H" at the arrival of the pulse to thereby cause the output to assume an "H" state. Thus, the flip-flop F₄ also remains at its reset state. As the result of the above successive operations, the connection points J₁ and J₂ take "H" and the connection points J₃ and J₄ take "L". The audio signal applied through the terminal A₁ is taken off from the terminal A₂ divided by the ratio between the resistance value of R₁ and that of the resistors R₂ and R₃. Therefore, the signal level at the terminal A₂ becomes higher than that obtained in the state described in item (1) above.

(3) A state when the second pulse is applied to the terminal U₁

The circuit operations are similar as those described in item (1) above, and the flip-flops F₁, F₂ and F₃ are set while only the flip-flop F₄ remains reset. Therefore, only the terminal J₄ is grounded and the voltage level of the signal applied to the input terminal A₁ is divided by the ratio between the resistance value of R₁ and that of the sum of the resistors R₂, R₃ and R₄.

(4) A state when the third pulse is applied to the terminal U₁

The flip-flop F₄ turns into the set state and thus all of the flip-flops are now brought into the set state. Therefore, the signal applied through the input terminal A₁, is divided by the ratio between the resistance value of R₁ and that of R₂, R₃, R₄ and R₅. Thereafter, the above set state is kept even when further pulses are applied to the terminal U₁.

(5) A state when a first pulse P₂ is applied to the terminal D₁

When a pulse P₂ arrives at the terminal D₁ under the state wherein all of the flip-flops are kept set, both of the set input terminal s₄₂ and the gate terminal g₄₂ in the gate circuit G₄₂ are set to "H" to develop an output signal at the "L" level at its output terminal. The gate circuit G₄₁, develops a "H" output since the set input terminal s₄₁ is again "L" although the gate terminal g₄₁ remains "H". Therefore, the flip-flop F₄ turns into the reset state. The outputs of the gate circuits G₃₂, G₂₂ and G₁₂ remain "H" in spite of the application of the pulse because each of the gate terminals g₃₂, g₂₂ and g₁₂ remains at the "L" level. Thus, the flip-flops F₁, F₂ and F₃ maintain their set state and, as the result, only the connection point J₄ is grounded. After the pulse P₂ has ended, the voltage at the "H" level developed at the terminal Q₃ is applied via the delay circuit T₄₂ to the gate terminal g₃₂ of the gate circuit G₃₂ to attain the same condition as described in item (3) above.

(6) A state when the second pulse P₂ is applied to the terminal D₁

The set terminal S₃₂ and the gate terminal g₃₂ of the gate circuit G₃₂ are set "H" to turn the output thereof to "L". Therefore, the flip-flop F₃ turns into the reset state. Since other flip-flops, F₁, F₂ and F₄ remain with their states unchanged, the connection points J₃ and J₄ are now grounded. After the end of the pulse P₂, the gate terminal g₄₁ of the gate circuit G₄₁ assumes the "L" state and the gate terminal g₂₂ of the gate circuit G₂₂ becomes "H", which is the same state as described in item (2) above.

(7) A state when the third pulse P₂ is applied to the terminal D₁

The output of the gate circuit G₂₂ is set to "L" to turn the flip-flop F₂ to the reset state. The other flip-flops F₁, F₃ and F₄ are kept in the preceeding states. Therefore, the connection point J₂ is grounded. After the end of the pulse, the gate terminal g₃₁ is set to "L" and the gate terminal g₁₂ is set to "H", which is the same as the initial state described in item (1) attained after the application of the power supply voltage.

(8) A state when the fourth pulse P₂ is applied to the terminal D₁

Since the gate terminal g₁₂ remains "H" and the set terminal s₁₂ is now set to "H", the gate circuit G₁₂ provides an output signal of the "L" level to thereby turn the flip-flop F₁ into the reset state. Accordingly, the terminal Q₁₁ becomes "L" and the connection point J₁ is grounded. Thus, the audio signal applied at the terminal A₁ is grounded and does not appear at the terminal A₂. This state is continued, thereafter, even when further pulses P₂ are applied to the terminal D₁.

The circuit operation has been described with reference to respective states set forth in each of the items (1) through (8). The output states of the flip-flops as described in each of the items are shown as a truth table in FIG. 2 and the states of the voltages set at each of the gate terminals and set terminals in the gate circuits where the operation of each of the flip-flops is stabilized, are illustrated in FIG. 3. It will easily be understood referring to FIG. 2 and FIG. 3, how the circuit shown in FIG. 1 changes its state from a certain established condition to another by way of the successive arrival of the pulses P₁ or P₂.

In the circuit illustrated in FIG. 1, a capacitor C₁ is connected between the set input terminal s₁ and ground, and the capacitors C₂, C₃ and C₄ are connected between each of the reset input terminals r₂, r₃ and r₄ of other flip-flops F₂, F₃ and F₄ and ground respectively. The capacitor C₁ thus connected, establishes an initial state wherein the flip-flop F₁ is preferably brought into the set state when the power source voltage is applied. In a modified circuit, the capacitor C₂ may be connected between the set input terminal s₂ and ground in a similar manner as the capacitor C₁ thereby preferably bringing both of the flip-flops F₁ and F₂ into the set state after the application of the power source voltage. In such a modified circuit, in other words, the audio signal applied to the terminal A₁ is at first taken off from the terminal A₂ as a level divided by the ratio between the resistance value of R₁ and that of the resistors R₂ and R₃. The audio signal to be taken off after the application of the power source voltage can thus be set at an intermediate level. This circuit is very convenient for a viewer because when applying the same to a volume control circuit in a television receiver, the volume can be controlled at the intermediate level when the power switch is turned to "on".

The circuit shown in FIG. 1 may be altered as shown in FIG. 4. The circuit will be described only with respect to the differences in comparison to the embodiment of FIG. 1. The audio signal is applied to a terminal A₁₁ and taken off from a terminal A₁₂. Since a further resistor R₅₅ is connected in the series, the signal level taken off from the output terminal A₁₂ is always kept at a certain level without decreasing to zero even when all of the connection points J₁₁ through J₁₄ are grounded. Transistors Tr₁, Tr₂, Tr₃ and Tr₄ are respectively connected between each of the output terminals Q₁₁, Q₂₁, Q₃₁ and Q₄₁ of the flip-flops and the connection points J₁₁, J₁₂, J₁₃ and J₁₄ corresponding thereto. These transistors operate as switching devices with each of their base electrodes being controlled by the output voltage of the flip-flops. The set input terminal s₁ of the flip-flop F₁ is directly connected to a common terminal D₁. No gate means are interposed therebetween and the reset terminal r₄ of the flip-flop F₄ is directly connected to the common terminal U₁ also with no gate means interposed therebetween. A gate circuit G₁₂ has a transistor Tr₁₂ the base of which is used as a gate terminal s₁₂, the emitter of which is used as a set terminal s₁₂ and the collector of which is used as an output terminal and supplied with a voltage B⁺ via a resistor R₇₂. The other gate circuits G₂₁, G₂₂, G₃₁, G₃₂, and G₄₁ have the same construction as the gate circuit G₁₂. The control signals P₁₁ and P₁₂ to be applied to input the terminals U₁ and D₁ are the respective pulses which have opposite polarities to those of the pulses P₁ and P₂ shown in FIG. 1. In the circuit shown in FIG. 4, capacitors C₁ and C₂ are respectively connected between the set input terminals s₁ and s₂, and the ground, and capacitors C₃ and C₄ are respectively connected between the reset input terminals r₃ and r₄ and ground. In the initial state where only the power source voltage is applied, the flip-flops F₁ and F₂ attain the set state and the flip-flops F₃ and F₄ attain the reset state, whereby the transistors Tr₁ and Tr₂ have a "H" base voltage and become saturated to conduct. On the other hand, the transistors Tr₃ and Tr₄ remain non-conductive. This means that the connection points J₁₁ and J₁₂ are grounded. Therefore, the audio signal applied through the terminal A₁₁ is taken off from the terminal A₁₂ divided by the ratio between the resistance value of the resistors R₅₃, R₅₄, R₅₅ and R₅₆ at a predetermined intermediate level in the range to be controlled. After the power source voltage is applied, each of the controlling operations of the circuit is started from the above described initial state.

Although the operation of the circuits shown in FIG. 1 and FIG. 4, has been described with reference to the audio signal as an example of the signal to be controlled, the signal may be any other AC current signal or may be a DC voltage. Also, reference has been made to for providing the resistors connected in series the connection points in the series with ground level or with certain reference voltage levels it will be appreciated that impedance elements having a capacitance and/or an inductance may be used instead of the resistors.

FIG. 5 shows a part of a circuit diagram in which impedance elements connected in series shown as blocks 1 to 4 are used instead of the resistors connected in series. The terminal A₁ in this embodiment is connected to a circuit which requires an impedance control.

FIG. 6 shows a part of a circuit diagram of another embodiment wherein a ladder type circuit network comprising impedance elements 11 to 19, is applied to the circuit shown in FIG. 1.

Although this invention has thus been described referring to the preferred embodiments thereof, it will be understood that it is intended to cover all modifications and equivalents within the scope of the appended claims. 

What is claimed is:
 1. A circuit arrangement for the digital control of analog output signal levels, comprising a plurality of impedance elements connected in series to form voltage divider means having a number of connection points between adjacent impedance elements, an analog input terminal and an analog output terminal connected to said voltage divider means, said circuit arrangement further comprising digital control circuit means including memory circuit stages corresponding in number to said number of connection points between adjacent impedance elements, each memory circuit stage having a setting input terminal, a resetting input terminal as well as first and second output terminals for providing different output states, means operatively connecting said first output terminal of each stage to the respective connecting point in said voltage divider means, setting and resetting circuit means operatively connected to the respective setting input terminal and to the respective resetting input terminal of the corresponding memory circuit stage, said setting and resetting circuit means having control input terminal means, first and second digital control signal input means operatively connected to said control input terminal means of said setting and resetting circuit means, first delay circuit means operatively connecting the first output terminal of a preceding memory circuit stage to the appropriate control input terminal means of the next following memory circuit stage, second delay circuit means operatively connecting the second output terminal of a following memory circuit stage to the appropriate control input terminal means of the next preceding memory circuit stage, and further delay circuit means operatively connected to selected ones of said setting and resetting input terminals of said memory circuit stages, whereby different potential levels may be applied to said connection points in response to digital control input signals supplied respectively to said second and first digital control signal input means.
 2. The circuit arrangement of claim 1, wherein said memory circuit stages comprise at least a first stage and a last stage, said setting and resetting circuit means comprising for each of said memory circuit stages a setting logic circuit gate connected to the setting input terminal of the corresponding stage and a resetting logic circuit gate connected to the resetting input terminal of the corresponding stage, said setting logic circuit gate of the first stage having two inputs connected to said first digital control signal input means, said resetting logic circuit gate of the last stage having two inputs connected to said second digital control signal input means, said resetting logic circuit gate of the first stage having a signal input connected to said second digital control signal input means and a gate input connected to the next stage, said setting logic circuit gate of the last stage having a signal input connected to said first digital control signal input means and a gate input connected to the preceding stage.
 3. The circuit arrangement of claim 2, wherein said logic circuit gates of memory circuit stages between said first and last stage have gate inputs connected to said second output terminal of an adjacent stage, and signal inputs connected respectively to said first and second digital control signal input means.
 4. The circuit arrangement of claim 1, wherein each of said memory circuit stages comprises an R-S flip-flop circuit.
 5. The circuit arrangement of claim 1, wherein each of said first and second delay circuit means comprises an integration circuit having a resistor and a capacitor.
 6. The circuit arrangement of claim 5, wherein, for charging the capacitor each of said integration circuits has a time constant which is greater than the pulse width and shorter than the pulse repetition interval of first and second digital control signals applied to said first and second digital control signal input means.
 7. The circuit arrangement of claim 6, wherein each of said further delay circuit comprises capacitor means connected between selected ones of the setting and resetting input terminals of said memory circuit stages and ground.
 8. The circuit arrangement of claim 1, wherein said means operatively connecting said first output terminal to the respective connecting point comprise a switching circuit connected between each of said first output terminals of said memory circuit stages and the respective connection point formed in said voltage divider means.
 9. The circuit arrangement of claim 1, wherein said memory circuit stages comprise at least a first stage and a last stage, wherein said setting circuit means of the first stage directly connect the setting input terminal of the first stage to said first digital control signal input means, and wherein said resetting circuit means of the last stage directly connect the resetting input terminal of said last stage to said second digital control signal input means.
 10. The circuit arrangement of claim 9, wherein each of said memory circuit stages comprises flip-flop circuit means including an R-S flip-flop circuit.
 11. The circuit arrangement of claim 10, wherein each of said first and second delay circuit means comprises an integration circuit having a resistor and a capacitor.
 12. The circuit arrangement of claim 11, wherein, for charging the capacitor, each of said integration circuits has a time constant which is greater than the pulse width and shorter than the pulse repetition interval of first and second digital control signals applied to said first and second digital control signal input means.
 13. The circuit arrangement of claim 12, wherein each of said further delay circuit means comprises capacitor means connected between selected ones of the setting and resetting input terminals of said memory circuit stages and ground. 